The proposal of the SPD router electronics

This block diagram shows proposal router electronics as it is created electronics group from Institute of Experimental physics in Kosice in collaboration with CERN group.

Source interface unit ( SIU ) and Short link mezanine  ( SLM ) components will be delivered from CERN group and installed to router board as mezanine card.

Signals used for SPD router /proposition/:

              L0                           for BUSY synchronization only        /cable/

           BUSY                                                                         /cable/

  TTC fiber signals:            - 40.08MHz clock

- BCR    (à BCN,ONUM)

- L1

- ECR    (à L1_ID)

- INIT

- L2a

- L2R

- CAL (?)

 VME controller is implemented in FPGA ( ALTERA EPM7064 ) , programmed in hardware description language VERILOG and simulated with  MAX PLUS + software  ( from ALTERA coorporation ).  VME controller manages read and write on VME bus.

 ROUTER controller  is implemented in FPGA ( ALTERA EP20KE ) , programmed in hardware description language AHDL and simulated with  Quartus software ( from ALTERA coorporation ).

ROUTER controller receive data from SPD detector through 6 Short link mezzanine cards. Data are formated, filtred and assigned identification trigger informations.

It create an arrange queues from different physical events. 

It manage a transmit over fiber optic to DAQ.

  SPY controller is implemented in FPGA ( ALTERA EPM3128A) , programmed in hardware description language AHDL and simulated with  MAX PLUS + software         ( from ALTERA coorporation ).

SPY controller manages wite a data samples running to DAQ system into SPY memory  and manages read out data samples.

SPY memory is high-seed (3.3V 32Kx36) synchronous pipelined dual-port RAM    ( IDT 70V3579S).

SPY memory look at on dates running from detector, so from SLM units. It made a data samples running to DAQ system. SPY memory is too for test purpose.

 JTAG controller

This block diagram is for partial testing this year, and than will be implement to SPD Router electronics.

  Proposed solution/implementation:

 -signals used      

                                                TRST

TCK

                                               TMS

                                                TDI

                                                TDO_ret

TRST_ret     

                                                TCK_ret

                                               TMS_ret       

- signals TRST_ret, TCK_ret, TMS_ret are interconected on chip with TRST, TCK, TMS. It safe same delay as will be TDO_ret.

 - 4 JTAG ports implemented in JTAG controller

 - FIFO_IN and FIFO_OUT are dual port FIFO memory ( read and write can ran with other clock – read and write cycle are independent ).

 - Data (macroinstruction) are saved in FIFO_IN memory and read out from FIFO_OUT memory through VME bus.

 - Macroinstructions are 32 bits words defined DATA_IN STRUCTURE  and DATA_OUT STRUCTURE..

 - STATUS have 32 bits ( 32 flags from controller state, clock speed, ………..)

JTAG controller  is implemented in FPGA ( ALTERA EP20KE) , programmed in hardware description language Verilog and simulated with  Quartus software ( from ALTERA coorporation ).                                          

  VME controller is implemented in FPGA ( ALTERA  EPM3128A) , programmed in hardware description language Verilog and simulated with  MAX PLUS +   software

 ( from ALTERA coorporation ).  

Design is comply with IEEE Standard Test Access Port and Boundary-Scan Architecture   ( IEEE Std 1149.1-1990 ).

Status of the Router electronics for Alice SPD ( February 2001 ).

A/     Main Controller

Status: Altera code written  ( in  AHDL)  for the interface

between the detector and the router as defined in April 2000.

Next action/step: Cern group is working on new interface.

                  Once new interface is defined the code need to be

                  adopted.

B/    Configuration controller

Status: Altera code written (in Verilog HDL) and extensively simulated.

Next action/step: Special configuration board to be produced in Kosice

                  and to be tested at Cern.

C/     Spy memory controller

Status: Altera code written (in AHDL).